LAN9353 Datasheet, PDF (290/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.7.3.4 Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0)
Register #:
1805h
Size:
32 bits
This register is used in conjunction with the Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1) to read
the ALR table. It contains the first 32 bits of the ALR entry and is loaded via the Get First Entry or Get Next Entry com-
mands in the Switch Engine ALR Command Register (SWE_ALR_CMD). This register is only valid when either of the
Valid or End of Table bits in the Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1) are set.
Bits
Description
31:0 MAC Address
This field contains the first 32 bits of the ALR entry. These bits correspond to
the first 32 bits of the MAC address. Bit 0 holds the LSB of the first byte (the
multicast bit).
Type
RO
Default
00000000h
DS00001925A-page 290
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