LAN9353 Datasheet, PDF (286/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.7.3 SWITCH ENGINE CSRS
This section details the Switch Engine related CSRs. These registers allow configuration and monitoring of the various
Switch Engine components including the ALR, VLAN, Port VID and DIFFSERV tables. A list of the general switch CSRs
and their corresponding register numbers is included in Table 10-9.
10.7.3.1 Switch Engine ALR Command Register (SWE_ALR_CMD)
Register #:
1800h
Size:
32 bits
This register is used to manually read and write for MAC addresses from/into the ALR table. Setting any bit in this reg-
ister will set the Operation Pending bit in the Switch Engine ALR Command Status Register (SWE_ALR_CMD_STS)
and perform the specified command. Only one bit should be set at a time.
For a read accesses (Get commands), the Operation Pending bit indicates when the command is finished. The Switch
Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0) and the Switch Engine ALR Read Data 1 Register
(SWE_ALR_RD_DAT_1) can then be read.
For write accesses (Make command), the Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0) and the
Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) should first be written with the MAC address and
data. The Operation Pending bit indicates when the command is finished.
Bits
Description
31:3 RESERVED
2
Make Entry
When set, the contents of SWE_ALR_WR_DAT_0 and SWE_ALR_WR_-
DAT_1 are written into the ALR table. The ALR logic determines the location
where the entry is written. This command can also be used to change or
delete a previously written or automatically learned entry.
This bit self-clears once the operation is complete as indicated by a low in the
Operation Pending bit in the Switch Engine ALR Command Status Register
(SWE_ALR_CMD_STS).
This bit has no affect when written low.
1
Get First Entry
When set, the ALR read pointer is reset to the beginning of the ALR table and
the ALR table is searched for the first valid entry, which is loaded into the
SWE_ALR_RD_DAT_0 and SWE_ALR_RD_DAT_1 registers.
This bit self-clears once the operation is complete as indicated by a low in the
Operation Pending bit in the Switch Engine ALR Command Status Register
(SWE_ALR_CMD_STS).
This bit has no affect when written low.
0
Get Next Entry
When set, the next valid entry in the ALR MAC address table is loaded into
the SWE_ALR_RD_DAT_0 and SWE_ALR_RD_DAT_1 registers.
This bit self-clears once the operation is complete as indicated by a low in the
Operation Pending bit in the Switch Engine ALR Command Status Register
(SWE_ALR_CMD_STS).
This bit has no affect when written low.
Type
RO
R/W
SC
R/W
SC
R/W
SC
Default
-
0b
0b
0b
DS00001925A-page 286
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