LAN9353 Datasheet, PDF (276/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.7.2.29 Port x MAC Transmit Deferred Count Register (MAC_TX_DEFER_CNT_x)
Register #:
Port0: 0451h
Port1: 0851h
Port2: 0C51h
Size:
32 bits
This register provides a counter deferred packets. The counter is cleared upon being read.
Bits
Description
31:0 TX Deferred
Count of packets that were available for transmission but were deferred on
the first transmit attempt due to network traffic (either on receive or prior
transmission). This counter is not incremented on collisions. This counter is
incremented only in half-duplex operation.
Note: This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100 Mbps is approximately 481 hours.
Type
RC
10.7.2.30 Port x MAC Transmit Pause Count Register (MAC_TX_PAUSE_CNT_x)
Default
00000000h
Register #:
Port0: 0452h
Port1: 0852h
Port2: 0C52h
Size:
32 bits
This register provides a counter of transmitted pause packets. The counter is cleared upon being read.
Bits
Description
31:0 TX Pause
Count of pause packets transmitted.
Note: This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100 Mbps is approximately 481 hours.
Type
RC
Default
00000000h
DS00001925A-page 276
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