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| LAN9353 Datasheet, PDF (389/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII | |||
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LAN9353
14.4.1.3 Port 0 PHY Mode SMI Managed
In this mode, Physical PHYs A and B, Virtual PHY 0 and the SMI slave block are accessed via an external master
attached to the Port 0 MII pins. The Virtual PHY 0 parallel interface is accessible via the SMI slave and the EEPROM
Loader. The PMI parallel interface is accessible via the SMI slave and the EEPROM Loader. However, this block is not
used in this mode once device initialization is complete.
Figure 14-5 details the MII Mode Multiplexer management path connections for this mode.
FIGURE 14-5:
MII MUX MANAGEMENT PATH CONNECTIONS - PHY MODE SMI MANAGED
mdi SMI Slave
mdo
mdc
Parallel
Master
mdio_dir
mdi Virtual PHY 0
mdo
mdc
Parallel
Slave
mdio_dir
mdi PHY B
mdo
mdio_dir
mdc
mdi PHY A
mdo
mdio_dir
mdc
Management
Mode Selection
MII Pins
mdio_dir
p
mdo
i
n
mdi
m
mdc_dir
u
x
mdc_out
i
n
mdc_in
g
P0_MDIO
P0_MDC
Management
Mode Selection
mdo mdc mdi mdio_en_n
PMI
Parallel Slave
ï£ 2015 Microchip Technology Inc.
DS00001925A-page 389
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