LAN9353 Datasheet, PDF (356/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
This data is first preceded with a Burst Sequence Valid Flag (EEPROM byte 17). If this byte has a value of A5h, the data
that follows is recognized as a sequence of bursts. Otherwise, the EEPROM Loader is finished, will go into a wait state
and clear the EEPROM Controller Busy (EPC_BUSY) bit in the EEPROM Command Register (E2P_CMD). This can
optionally generate an interrupt.
The data at EEPROM byte 18 and above should be formatted in a sequence of bursts. The first byte is the total number
of bursts. Following this is a series of bursts, each consisting of a starting address, count and the count x 4 bytes of data.
This results in the following formula for formatting register data:
8 bits number_of_bursts
repeat (number_of_bursts)
16 bits {starting_address[9:2] / count[7:0]}
repeat (count)
8 bits data[31:24], 8 bits data[23:16], 8 bits data[15:8], 8 bits data[7:0]
Note: The starting address is a DWORD address. Appending two 0 bits will form the register address.
As an example, the following is a 3 burst sequence, with 1, 2 and 3 DWORDs starting at register addresses 40h, 80h
and C0h respectively:
A5h, (Burst Sequence Valid Flag)
3h, (number_of_bursts)
16{10h, 1h}, (starting_address1 divided by 4 / count1)
11h, 12h, 13h, 14h, (4 x count1 of data)
16{20h, 2h}, (starting_address2 divided by 4 / count2)
21h, 22h, 23h, 24h, 25h, 26h, 27h, 28h, (4 x count2 of data)
16{30h, 3h}, (starting_address3 divided by 4 / count3)
31h, 32h, 33h, 34h, 35h, 36h, 37h, 38h, 39h, 3Ah, 3Bh, 3Ch (4 x count3 of data)
In order to avoid overwriting the Switch CSR interface or PHY Management Interface, the EEPROM Loader waits until
the following bits are cleared before performing any register write:
• CSR Busy (CSR_BUSY) bit of the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD)
• MII Busy (MIIBZY) bit of the PHY Management Interface Access Register (PMI_ACCESS)
The EEPROM Loader checks that the EEPROM address space is not exceeded. If so, it will stop and set the EEPROM
Loader Address Overflow (LOADER_OVERFLOW) bit in the EEPROM Command Register (E2P_CMD). The address
limit is based on the eeprom_size_strap which specifies a range of sizes. The address limit is set to the largest value of
the specified range.
12.4.6 EEPROM LOADER FINISHED WAIT-STATE
Once finished with the last burst, the EEPROM Loader will go into a wait-state and the EEPROM Controller Busy
(EPC_BUSY) bit of the EEPROM Command Register (E2P_CMD) will be cleared. This can optionally generate an inter-
rupt.
12.5 I²C Master EEPROM Controller Registers
This section details the directly addressable I²C Master EEPROM Controller related System CSRs. These registers
should only be used if an EEPROM has been connected to the device. For an overview of the entire directly addressable
register map, refer to Section 5.0, "Register Map," on page 41.
DS00001925A-page 356
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