LAN9353 Datasheet, PDF (309/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.7.3.21 Switch Engine Priority to Queue Register (SWE_PRI_TO_QUE)
Register #:
1845h
Size:
32 bits
This register specifies the Traffic Class table that maps the packet priority into the egress queues.
Bits
Description
31:16
15:14
RESERVED
Priority 7 traffic Class
These bits specify the egress queue that is used for packets with a priority of
7.
13:12
Priority 6 traffic Class
These bits specify the egress queue that is used for packets with a priority of
6.
11:10
Priority 5 traffic Class
These bits specify the egress queue that is used for packets with a priority of
5.
9:8 Priority 4 traffic Class
These bits specify the egress queue that is used for packets with a priority of
4.
7:6 Priority 3 traffic Class
These bits specify the egress queue that is used for packets with a priority of
3.
5:4 Priority 2 traffic Class
These bits specify the egress queue that is used for packets with a priority of
2.
3:2 Priority 1 traffic Class
These bits specify the egress queue that is used for packets with a priority of
1.
1:0 Priority 0 traffic Class
These bits specify the egress queue that is used for packets with a priority of
0.
Type
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
-
11b
11b
10b
10b
01b
00b
00b
01b
 2015 Microchip Technology Inc.
DS00001925A-page 309