LAN9353 Datasheet, PDF (348/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
Figure 12-3 illustrates a typical I²C EEPROM addressing bit order for single and double byte addressing.
FIGURE 12-3:
I²C EEPROM ADDRESSING
Control Byte
Address Byte
S
1
0
1
0
A
1
0
A
9
A
8
0
A
C
K
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
C
K
Chip / Block R/~W
Select Bits
Single Byte Addressing
Control Byte
Address High
Byte
Address Low
Byte
S
1
0
1
0
0
0
0
0
A
C
K
A
1
5
A
1
4
A
1
3
A
1
2
A
1
1
A
1
0
A
9
A
8
A
C
K
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
C
K
Chip / Block R/~W
Select Bits
Double Byte Addressing
12.3.2 I²C EEPROM BYTE READ
Following the device addressing, a data byte may be read from the EEPROM by outputting a start condition and control
byte with a control code of 1010b, chip/block select bits as described in Section 12.3.1 and the R/~W bit high. The
EEPROM will respond with an acknowledge, followed by 8 bits of data. If the EEPROM slave fails to send an acknowl-
edge, then the sequence is aborted (a start condition and a stop condition are sent) and the EEPROM Controller Tim-
eout (EPC_TIMEOUT) bit in the EEPROM Command Register (E2P_CMD) is set. The I²C master then sends a no-
acknowledge, followed by a stop condition.
Figure 12-4 illustrates a typical I²C EEPROM byte read for single and double byte addressing.
FIGURE 12-4:
I²C EEPROM BYTE READ
Control Byte
Data Byte
A
C
K
S
1
0
1
0
A
1
0
A
9
A
8
1
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
P
Chip / Block R/~W
Select Bits
Single Byte Addressing Read
Control Byte
Data Byte
A
C
K
S
1
0
1
0
0
0
0
1
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
P
Chip / Block R/~W
Select Bits
Double Byte Addressing Read
For a register level description of a read operation, refer to Section 12.3.7, "I2C Master EEPROM Controller Operation,"
on page 351.
12.3.3 I²C EEPROM SEQUENTIAL BYTE READS
Following the device addressing, data bytes may be read sequentially from the EEPROM by outputting a start condition
and control byte with a control code of 1010b, chip/block select bits as described in Section 12.3.1 and the R/~W bit
high. The EEPROM will respond with an acknowledge, followed by 8 bits of data. If the EEPROM slave fails to send an
acknowledge, then the sequence is aborted (a start condition and a stop condition are sent) and the EEPROM Controller
Timeout (EPC_TIMEOUT) bit in the EEPROM Command Register (E2P_CMD) is set. The I²C master then sends an
acknowledge and the EEPROM responds with the next 8 bits of data. This continues until the last desired byte is read,
at which point the I²C master sends a no-acknowledge (instead of the acknowledge), followed by a stop condition.
DS00001925A-page 348
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