LAN9353 Datasheet, PDF (413/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
15.5 1588 GPIOs
In addition to time stamping PTP packets, the 1588 Clock value can be saved into a set of clock capture registers based
on the GPIO inputs. The GPIO inputs can also be used to clear the 1588 Clock Target compare event interrupt. When
configured as outputs, GPIOs can be used to output a signal based on an 1588 Clock Target compare events.
Note: The IEEE 1588 Unit supports up to 8 GPIO signals.
15.5.1 1588 GPIO INPUTS
15.5.1.1 GPIO Event Clock Capture
When the GPIO pins are configured as inputs, and enabled with the GPIO Rising Edge Capture Enable 7-0 (GPIO_RE_-
CAPTURE_ENABLE[7:0]) or GPIO Falling Edge Capture Enable 7-0 (GPIO_FE_CAPTURE_ENABLE[7:0]) bits in the
1588 GPIO Capture Configuration Register (1588_GPIO_CAP_CONFIG), a rising or falling edge, respectively, will cap-
ture the 1588 Clock into the 1588 GPIO x Rising Edge Clock Seconds Capture Register (1588_GPIO_RE_-
CLOCK_SEC_CAP_x) and the 1588 GPIO x Rising Edge Clock NanoSeconds Capture Register
(1588_GPIO_RE_CLOCK_NS_CAP_x) or 1588 GPIO x Falling Edge Clock Seconds Capture Register (1588_GPI-
O_FE_CLOCK_SEC_CAP_x) and the 1588 GPIO x Falling Edge Clock NanoSeconds Capture Register (1588_GPI-
O_FE_CLOCK_NS_CAP_x) where x equals the number of the active GPIO input.
GPIO inputs must be stable for greater than 40 ns to be recognized as capture events and are edge sensitive.
The GPIO inputs have a fixed capture latency of 65 ns that can be accounted for by the Host driver. The GPIO inputs
have a capture latency uncertainty of +/-5 ns.
The corresponding, maskable, interrupt flags 1588 GPIO Rising Edge Interrupt (1588_GPIO_RE_INT[7:0]) or 1588
GPIO Falling Edge Interrupt (1588_GPIO_FE_INT[7:0]) in the 1588 Interrupt Status Register (1588_INT_STS) will also
be set. This is in addition to the interrupts available in the General Purpose I/O Interrupt Status and Enable Register
(GPIO_INT_STS_EN).
A lock enable bit is provided for each timestamp enabled GPIO, Lock Enable GPIO Rising Edge (LOCK_GPIO_RE) and
Lock Enable GPIO Falling Edge (LOCK_GPIO_FE) in the 1588 GPIO Capture Configuration Register (1588_GPIO_-
CAP_CONFIG), which prevents the corresponding GPIO clock capture registers from being overwritten if the GPIO
interrupt in 1588 Interrupt Status Register (1588_INT_STS) is already set.
15.5.1.2 GPIO Timer Interrupt Clear
The GPIO inputs can also be configured to clear the 1588 Timer Interrupt A (1588_TIMER_INT_A) or 1588 Timer Inter-
rupt B (1588_TIMER_INT_B) in the 1588 Interrupt Status Register (1588_INT_STS) by setting the corresponding
enable and select bits in the 1588 General Configuration Register (1588_GENERAL_CONFIG).
The polarity of the GPIO input is determined by the GPIO Interrupt/1588 Polarity 7-0 (GPIO_POL[7:0]) bits in the Gen-
eral Purpose I/O Configuration Register (GPIO_CFG).
GPIO inputs must be active for greater than 40 ns to be recognized as interrupt clear events and are edge sensitive.
15.5.2 1588 GPIO OUTPUTS
Upon detection of a Clock Target A or B compare event, the corresponding clock event channel can be configured to
output a 100 ns pulse, toggle its output, or reflect its 1588 Timer Interrupt bit. The selection is made using the Clock
Event Channel A Mode (CLOCK_EVENT_A) and Clock Event Channel B Mode (CLOCK_EVENT_B) bits of the 1588
General Configuration Register (1588_GENERAL_CONFIG).
A GPIO pin is configured as a 1588 event output by setting the corresponding 1588 GPIO Output Enable 7-0 (1588_G-
PIO_OE[7:0]) bits in the General Purpose I/O Configuration Register (GPIO_CFG). These bits override the GPIO Direc-
tion bits of the General Purpose I/O Data & Direction Register (GPIO_DATA_DIR) and allow for GPIO output generation
based on the 1588 Clock Target compare event. The choice of the event channel is controlled by the 1588 GPIO Chan-
nel Select 7-0 (GPIO_CH_SEL[7:0]) bits in the General Purpose I/O Configuration Register (GPIO_CFG).
Note: The 1588 GPIO Output Enable 7-0 (1588_GPIO_OE[7:0]) bits do not override the GPIO Buffer Type 7-0
(GPIOBUF[7:0]) in the General Purpose I/O Configuration Register (GPIO_CFG).
The clock event polarity, which determines whether the 1588 GPIO output is active high or active low, is controlled by
the GPIO Interrupt/1588 Polarity 7-0 (GPIO_POL[7:0]) bits in the General Purpose I/O Configuration Register (GPI-
O_CFG).
The GPIO outputs have a latency of approximately 40 ns when using “100 ns pulse” or “Interrupt bit” modes and 30 ns
when using “toggle” mode. On chip delays contribute an uncertainty of +/-4ns to these values.
 2015 Microchip Technology Inc.
DS00001925A-page 413