LAN9353 Datasheet, PDF (373/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
FIGURE 13-8:
TURBO MII INPUT TIMING (PHY MODE)
Px_INCLK
(output)
Px_IND[3:0],
Px_INER
t_hold
Px_INDV
t_clkp
t_clkh t_clkl
t_su t_hold
t_su t_hold
t_hold
t_su
TABLE 13-8: TURBO MII INPUT TIMING VALUES (PHY MODE)
Symbol
t_clkp
t_clkh
t_clkl
t_su
t_hold
Description
Px_INCLK period
Px_INCLK high time
Px_INCLK low time
Px_IND[3:0], Px_INER, Px_INDV setup time to
rising edge of Px_INCLK
Px_IND[3:0], Px_INER, Px_INDV hold time after
rising edge of Px_INCLK
Min
20
t_clkp * 0.4
t_clkp * 0.4
7.0
0
Max
-
t_clkp * 0.6
t_clkp * 0.6
-
-
Units
ns
ns
ns
ns
ns
Notes
Note 8
Note 8
Note 8: Timing was designed for system load between 10 pF and 15 pF.
13.4.5 RMII INTERFACE TIMING (MAC MODE)
This section specifies the RMII interface timing when in MAC mode. Both input and output clock modes are specified.
 2015 Microchip Technology Inc.
DS00001925A-page 373