LAN9353 Datasheet, PDF (141/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.2.20.14 PHY x Special Modes Register (PHY_SPECIAL_MODES_x)
Index (decimal): 18
Size:
This read/write register is used to control the special modes of the PHY.
16 bits
Bits
15:11
10
9:8
7:5
4:0
Description
RESERVED
100BASE-FX Mode (FX_MODE)
This bit enables 100BASE-FX Mode
Note:
FX_MODE cannot properly be changed with this bit. This bit must
always be written with its current value. Device strapping must be
used to set the desired mode.
RESERVED
PHY Mode (MODE[2:0])
This field controls the PHY mode of operation. Refer to Table 9-16 for a defi-
nition of each mode.
Note: This field should be written with its read value.
PHY Address (PHYADD)
The PHY Address field determines the MMI address to which the PHY will
respond and is also used for initialization of the cipher (scrambler) key. Each
PHY must have a unique address. Refer to Section 9.1.1, "PHY Addressing,"
on page 94 for additional information.
Note: No check is performed to ensure that this address is unique from
the other PHY addresses (PHY A, PHY B, and Virtual PHY 0).
Type
RO
R/W
NASR
Note 17
RO
R/W
NASR
Note 17
R/W
NASR
Note 17
Default
-
Note 18
-
Note 19
Note 20
Note 17: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Reg-
ister (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the
PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set.
Note 18: The default value of this bit is determined by the Fiber Enable strap (fx_mode_strap_1 for PHY A, fx_-
mode_strap_2 for PHY B).
Note 19: The default value of this field is determined by a combination of the configuration straps autoneg_strap_x,
speed_strap_x, and duplex_strap_x. If the autoneg_strap_x is 1, then the default MODE[2:0] value is 111b.
Else, the default value of this field is determined by the remaining straps. MODE[2]=0,
MODE[1]=(speed_strap_1 for PHY A, speed_strap_2 for PHY B), and MODE[0]=(duplex_strap_1 for PHY
A, duplex_strap_2 for PHY B). Refer to Section 7.0, "Configuration Straps," on page 67 for more information.
In 100BASE-FX mode, the default value of these bits is 010b or 011b. depending on the duplex configuration
strap.
Note 20: The default value of this field is determined per Section 9.1.1, "PHY Addressing," on page 94.
TABLE 9-16: MODE[2:0] DEFINITIONS
MODE[2:0]
Mode Definitions
000
10BASE-T Half Duplex. Auto-Negotiation disabled.
001
10BASE-T Full Duplex. Auto-Negotiation disabled.
 2015 Microchip Technology Inc.
DS00001925A-page 141