LAN9353 Datasheet, PDF (355/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
12.4.2 EEPROM VALID FLAG
Following the release of RST#, POR, DIGITAL_RST or a RELOAD command, the EEPROM Loader starts by reading
the first byte of data from the EEPROM. If the value of A5h is not read from the first byte, the EEPROM Loader will load
the current configuration strap values into the registers, restart PHY Auto-negotiation and then terminate, clearing the
EEPROM Controller Busy (EPC_BUSY) bit in the EEPROM Command Register (E2P_CMD). Otherwise, the EEPROM
Loader will continue reading sequential bytes from the EEPROM.
12.4.3 MAC ADDRESS
The next six bytes in the EEPROM, after the EEPROM Valid Flag, are written into the Switch Fabric MAC Address High
Register (SWITCH_MAC_ADDRH) and Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL). The
EEPROM bytes are written into the MAC address registers in the order specified in Table 12-3.
12.4.4 SOFT-STRAPS
The 7^th byte of data to be read from the EEPROM is the Configuration Strap Values Valid Flag. If this byte has a value
of A5h, the next 9 bytes of data (8-16) are written into the configuration strap registers per the assignments detailed in
Table 12-4.
If the flag byte is not A5h, these next 9 bytes are skipped (they are still read to maintain the data burst, but are dis-
carded). However, the current configuration strap values are still loaded into the registers and the PHY Auto-negotiation
is still restarted. Refer to Section 7.0, "Configuration Straps," on page 67 for more information on configuration straps.
Note: Bit locations in Table 12-4 that do not define a configuration strap must be written as 0.
TABLE 12-4: EEPROM CONFIGURATION BITS
Byte/Bit
Byte 8
Byte 9
Byte 10
Byte 11
Byte 12
Byte 13
Byte 14
Byte 15
Byte 16
7
BP_EN_
strap_1
BP_EN_
strap_2
1588_
enable_
strap
I2C_addr_
override_
strap
6
FD_FC_
strap_1
FD_FC_
strap_2
I2C_
address_
strap[6]
5
manual_
FC_strap_1
4
manual_m-
dix_strap_1
manual_
FC_strap_2
BP_EN_
strap_0
manual_m-
dix_strap_2
FD_FC_
strap_0
LED_fun_
strap[2]
LED_en_
strap[5]
I2C_
address_
strap[5]
LED_fun_
strap[1]
LED_en_
strap[4]
I2C_
address_
strap[4]
3
auto_mdix-
_strap_1
auto_mdix-
_strap_2
manual_F-
C_strap_0
LED_fun_
strap[0]
LED_en_
strap[3]
I2C_
address_
strap[3]
2
speed_
strap_1
speed_pol_
strap_1
speed_
strap_2
speed_
strap_0
speed_pol_
strap_0
EEE_
enable_
strap_2
LED_en_
strap[2]
I2C_
address_
strap[2]
1
0
duplex_
strap_1
duplex-
_pol_strap_
1
duplex_
strap_2
duplex_
strap_0
duplex-
_pol_strap_
0
EEE_
enable_
strap_1
LED_en_
strap[1]
I2C_
address_
strap[1]
autoneg_
strap_1
autoneg_
strap_2
SQE_test_
dis-
able_strap_0
EEE_
enable_
strap_0
LED_en_
strap[0]
I2C_
address_
strap[0]
12.4.5 REGISTER DATA
Optionally following the configuration strap values, the EEPROM data may be formatted to allow access to the device’s
parallel, directly writable registers. Access to indirectly accessible registers is achievable with an appropriate sequence
of writes (at the cost of EEPROM space).
 2015 Microchip Technology Inc.
DS00001925A-page 355