LAN9353 Datasheet, PDF (512/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
20.6.2 POWER SEQUENCING TIMING
These diagrams illustrates the device power sequencing requirements. The VDDIO, VDD33, VDD33TXRX1,
VDD33TXRX2, VDD33BIAS and magnetics power supplies must all reach operational levels within the specified time
period t_pon. When operating with the internal regulators disabled, VDDCR, OSCVDD12, VDD12TX1 and VDD12TX2 are
also included into this requirement.
In addition, once the VDDIO power supply reaches 1.0 V, it must reach 80% of its operating voltage level (1.44 V when
operating at 1.8 V, 2.0 V when operating at 2.5 V, 2.64 V when operating at 3.3 V) within an additional 15ms. This
requirement can be safely ignored if using an external reset as shown in Section 20.6.3, "Reset and Configuration Strap
Timing".
Device power supplies can turn off in any order provided they all reach 0 volts within the specified time period t_poff.
FIGURE 20-2:
POWER SEQUENCE TIMING - INTERNAL REGULATORS
t_pon
t_poff
VDDIO
Magnetics
Power
VDD33, VDD33BIAS,
VDD33TXRX1, VDD33TXRX2
FIGURE 20-3:
POWER SEQUENCE TIMING - EXTERNAL REGULATORS
t_pon
t_poff
VDDIO
Magnetics
Power
VDD33, VDD33BIAS,
VDD33TXRX1, VDD33TXRX2
VDDCR, OSCVDD12,
VDD12TX1, VDD12TX2
TABLE 20-10: POWER SEQUENCING TIMING VALUES
Symbol
t_pon
t_poff
Description
Power supply turn on time
Power supply turn off time
Min
Typ
Max Units
-
-
50
ms
-
-
500
ms
DS00001925A-page 512
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