LAN9353 Datasheet, PDF (95/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

• Wake on LAN (WoL)
• Resets
• Link Integrity Test
• Cable Diagnostics
• Loopback Operation
• 100BASE-FX Far End Fault Indication
A block diagram of the main components of each PHY can be seen in Figure 9-1.
FIGURE 9-1:
PHYSICAL PHY BLOCK DIAGRAM
LAN9353
To Port x
MII
Switch Fabric MAC
To MII Mux
MDIO
Auto-
Negotiation
MII
MAC
Interface
PHY Management
Control
Registers
Interrupts
10/100
Transmitter
10/100
Reciever
To System
Interrupt Controller
HP Auto-MDIX
TXPx/TXNx
RXPx/RXNx
To External
Port x Ethernet Pins
PLL
From
System Clocks Controller
 2015 Microchip Technology Inc.
DS00001925A-page 95