LAN9353 Datasheet, PDF (341/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
11.3 I²C Slave Operation
When in I²C managed mode, the I²C slave interface is used for CPU management of the device. All system CSRs are
accessible to the CPU in these modes. I²C mode is selected when the serial_mngt_mode_strap configuration strap is
set to 1b. The I²C slave controller implements the low level I²C slave serial interface (start and stop condition detection,
data bit transmission and reception and acknowledge generation and reception), handles the slave command protocol
and performs system register reads and writes. The I²C slave controller conforms to the NXP I²C-Bus Specification.
The I²C slave serial interface consists of a data wire (I2CSDA) and a serial clock (I2CSCL). The serial clock is driven
by the master, while the data wire is bi-directional. Both signals are open-drain and require external pull-up resistors.
The I²C slave serial interface supports the standard-mode speed of up to 100 kHz and the fast-mode speed of 400 kHz.
Refer to the NXP I²C-Bus Specification for detailed I²C timing information with the following modifications:
• tVD;DAT maximum (SDA data output valid from SCL falling) is 3000ns and 700ns for standard and fast modes
respectively.
• tVD;ACK maximum (SDA acknowledge output valid from SCL falling) is 3000ns and 700ns for standard and fast
modes respectively.
• tSP maximum (input spike suppression on SCL and SDA) is 100ns.
• tHD;DAT minimum (SDA data and acknowledge output hold from SCL falling) is 100ns.
11.3.1 I²C SLAVE COMMAND FORMAT
The I²C slave serial interface supports single register and multiple register read and write commands. A read or write
command is started by the master first sending a start condition, followed by a control byte. The control byte consists of
a 7-bit slave address and a 1-bit read/write indication (R/~W). The default slave address used by the device is
0001010b, written as SA6 (first bit on the wire) through SA0 (last bit on the wire). Alternatively, the I²C slave address
may be configured to another address by setting the I2C_addr_override_strap and configuring the I2C_ad-
dress_strap[6:0] with the desired value. Assuming the slave address in the control byte matches this address, the con-
trol byte is acknowledged by the device. Otherwise, the entire sequence is ignored until the next start condition. The I²C
command format can be seen in Figure 11-2.
If the read/write indication (R/~W) in the control byte is a 0 (indicating a potential write), the next byte sent by the master
is the register address. After the address byte is acknowledged by the device, the master may either send data bytes
to be written or it may send another start condition (to start the reading of data) or a stop condition. The latter two will
terminate the current write (without writing any data), but will have the affect of setting the internal register address which
will be used for subsequent reads.
If the read/write indication in the control byte is a 1 (indicating a read), the device will start sending data following the
control byte acknowledgment.
Note: All registers are accessed as DWORDs. Appending two 0 bits to the address field will form the register
address. Addresses and data are transferred MSB first. Data is transferred MSB first (little endian).
FIGURE 11-2:
I²C SLAVE ADDRESSING
Control Byte
Address Byte
S
S
A
6
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
S
A
0
0
A
C
K
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
C
K
*
R/~W
Start or
Stop or
Data [31]
 2015 Microchip Technology Inc.
DS00001925A-page 341