LAN9353 Datasheet, PDF (80/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 7-2: HARD-STRAP CONFIGURATION STRAP DEFINITIONS (CONTINUED)
Strap Name
P0_mode_strap[1:0]
Description
Pins
Switch Port 0 Mode Strap: Configures the mode of opera-
tion for Port 0.
00 = MII MAC Mode
01 = MII PHY Mode
10 = RMII MAC Mode
11 = RMII PHY Mode
P1_INTPHY :
P0_MODE3 :
P0_MODE2
These operating modes result from the following mapping:
P1_INTPHY
(see note)
1
1
1
0
1
0
P0_MODE[3:2] P0_mode_strap[1:0]
00
01
10
x0 (see note)
11
x1 (see note)
00 (MII MAC)
01 (MII PHY)
10 (RMII MAC)
11 (RMII PHY)
Note: P1_INTPHY equal to 0 forces RMII remapping
mode which forces Port 0 into RMII mode.
See Table 7-3 for the combined Port 0 mode strapping.
P0_rmii_clock_dir_strap
P0_clock_strength_strap
Switch Port 0 RMII Clock Direction Strap: Configures the
default value of the RMII Clock Direction bit in the (x=0) Port
x Virtual PHY Special Control/Status Register (VPHY_SPE-
CIAL_CONTROL_STATUS_x).
P0_MODE1
0 = Input
1 = Output
See Table 7-3 for the combined Port 0 mode strapping.
Switch Port 0 Clock Strength Strap: Configures the default
value of the RMII/Turbo MII Clock Strength bit in the (x=0)
Port x Virtual PHY Special Control/Status Register
(VPHY_SPECIAL_CONTROL_STATUS_x)
P0_MODE0
0 = 12ma
1 = 16ma
See Table 7-3 for the combined Port 0 mode strapping.
DS00001925A-page 80
 2015 Microchip Technology Inc.