LAN9353 Datasheet, PDF (349/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
Figure 12-5 illustrates a typical I²C EEPROM sequential byte reads for single and double byte addressing.
FIGURE 12-5:
I²C EEPROM SEQUENTIAL BYTE READS
... ^{Control Byte}
Data Byte
Data Byte
A
C
K
S
1
0
1
0
A
1
0
A
9
A
8
1
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
DD
76
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
Data Byte
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
P
K
Chip / Block R/~W
Select Bits
Single Byte Addressing Sequential Reads
Control Byte
Data Byte
Data Byte
Data Byte
... ^A
C
K
S
1
0
1
0
0
0
0
1
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
DD
76
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
P
K
Chip / Block R/~W
Select Bits
Double Byte Addressing Sequential Reads
Sequential reads are used by the EEPROM Loader. Refer to Section 12.4, "EEPROM Loader" for additional information.
For a register level description of a read operation, refer to Section 12.3.7, "I2C Master EEPROM Controller Operation,"
on page 351.
12.3.4 I²C EEPROM BYTE WRITES
Following the device addressing, a data byte may be written to the EEPROM by outputting the data after receiving the
acknowledge from the EEPROM. The data byte is acknowledged by the EEPROM slave and the I²C master finishes
the write cycle with a stop condition. If the EEPROM slave fails to send an acknowledge, then the sequence is aborted
(a start condition and a stop condition are sent) and the EEPROM Controller Timeout (EPC_TIMEOUT) bit in the
EEPROM Command Register (E2P_CMD) is set.
Following the data byte write cycle, the I²C master will poll the EEPROM to determine when the byte write is finished.
After meeting the minimum bus free time, a start condition is sent followed by a control byte with a control code of 1010b,
chip/block select bits low (since they are don’t cares) and the R/~W bit low. If the EEPROM is finished with the byte
write, it will respond with an acknowledge. Otherwise, it will respond with a no-acknowledge and the I²C master will issue
a stop and repeat the poll. If the acknowledge does not occur within 30 ms, a timeout occurs (a start condition and a
stop condition are sent) and the EEPROM Controller Timeout (EPC_TIMEOUT) bit in the EEPROM Command Register
(E2P_CMD) is set. The check for timeout is only performed following each no-acknowledge, since it may be possible
that the EEPROM write finished before the timeout but the 30 ms expired before the poll was performed (due to the bus
being used by another master).
Once the I²C master receives the acknowledge, it concludes by sending a start condition, followed by a stop condition,
which will place the EEPROM into standby.
Figure 12-6 illustrates a typical I²C EEPROM byte write.
FIGURE 12-6:
I²C EEPROM BYTE WRITE
Data Cycle
Poll Cycle
Poll Cycle
Poll Cycle
... ... _... ^{Data Byte}
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
P
Control Byte
S
1
0
1
0
0
0
0
0
A
C
P
K
Control Byte
S
1
0
1
0
0
0
0
0
A
C
P
K
Control Byte
Conclude
A
S1 0 1 0 0 0 0 0CSP
K
bus
Chip / Block R
bus
Chip / Block R
bus
Chip / Block R
free
Select Bits /
free
Select Bits /
free
Select Bits /
time
~
time
~
time
~
W
W
W
 2015 Microchip Technology Inc.
DS00001925A-page 349