LAN9353 Datasheet, PDF (182/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
The emulated link partner default advertised abilities in the Port x Virtual PHY Auto-Negotiation Link Partner Base Page
Ability Register (VPHY_AN_LP_BASE_ABILITY_x) are dependent on the duplex_strap_x (duplex_strap_0 for Virtual
PHY 0, duplex_strap_1 for Virtual PHY 1) and speed_strap_x (speed_strap_0 for Virtual PHY 0, speed_strap_1 for Vir-
tual PHY 1) configuration straps as described in Table 9-23 of Section 9.3.5.6, "Port x Virtual PHY Auto-Negotiation Link
Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY_x)," on page 196.
Note: The duplex_strap_x and speed_strap_x inputs are considered to be static. Auto-Negotiation is not automat-
ically re-evaluated if these inputs are changed.
Neither the Virtual PHY or the emulated link partner support next page capability, remote faults, or 100BASE-T4.
If there is at least one common selection between the emulated link partner and the Virtual PHY advertised abilities,
then the Auto-Negotiation succeeds, the Link Partner Auto-Negotiation Able bit of the Port x Virtual PHY Auto-Negotia-
tion Expansion Register (VPHY_AN_EXP_x) is set, and the technology ability bits in the Port x Virtual PHY Auto-Nego-
tiation Link Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY_x) are set to indicate the emulated link
partners abilities.
Note:
For the Virtual PHY, the Auto-Negotiation register bits (and management of such) are used by the MAC
driver, so the perception of local and link partner is reversed. The local device is the MAC, while the link
partner is the switch fabric. This is consistent with the intention of the Virtual PHY.
9.3.1.1 Parallel Detection
In the event that there are no common bits between the advertised ability and the emulated link partners ability, Auto-
Negotiation fails and emulated parallel detect is used. In this case, the Link Partner Auto-Negotiation Able bit in the Port
x Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP_x) will be cleared, and the communication set to
half-duplex. The speed is determined by the speed_strap_x (speed_strap_0 for Virtual PHY 0, speed_strap_1 for Virtual
PHY 1) configuration strap. Only one of the technology ability bits in the Port x Virtual PHY Auto-Negotiation Link Partner
Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY_x) will be set, indicating the emulated parallel detect result.
9.3.1.2 Disabling Auto-Negotiation
Auto-Negotiation can be disabled in the Virtual PHY by clearing the Auto-Negotiation (VPHY_AN) bit of the Port x Virtual
PHY Basic Control Register (VPHY_BASIC_CTRL_x). The Virtual PHY will then force its speed of operation to reflect
the speed (Speed Select LSB (VPHY_SPEED_SEL_LSB)) and duplex (Duplex Mode (VPHY_DUPLEX)) of the Port x
Virtual PHY Basic Control Register (VPHY_BASIC_CTRL_x). The speed and duplex bits in the Port x Virtual PHY Basic
Control Register (VPHY_BASIC_CTRL_x) are ignored when Auto-Negotiation is enabled.
9.3.1.3 Virtual PHY Pause Flow Control
The Virtual PHY supports pause flow control per the IEEE 802.3 specification. The Virtual PHY’s advertised pause flow
control abilities are set via the Symmetric Pause and Asymmetric Pause bits of the Port x Virtual PHY Auto-Negotiation
Advertisement Register (VPHY_AN_ADV_x). This allows the Virtual PHY to advertise its flow control abilities and Auto-
Negotiate the flow control settings with the emulated link partner. The default values of these bits are as shown in Sec-
tion 9.3.5.5, "Port x Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV_x)," on page 194.
The symmetric/asymmetric pause ability of the emulated link partner is based upon the advertised pause flow control
abilities of the Virtual PHY as indicated in the Symmetric Pause and Asymmetric Pause bits of the Port x Virtual PHY
Auto-Negotiation Advertisement Register (VPHY_AN_ADV_x). Thus, the emulated link partner always accommodates
the asymmetric/symmetric pause ability settings requested by the Virtual PHY, as shown in Table 9-22, “Emulated Link
Partner Pause Flow Control Ability Default Values,” on page 198.
The pause flow control settings may also be manually set via the Port 0 Manual Flow Control Register (MANUAL_FC_0)
(port 0) or Port 1 Manual Flow Control Register (MANUAL_FC_1) (port 1). This register allows the Switch Fabric port
flow control settings to be manually set when Auto-Negotiation is disabled or the Port 0 Full-Duplex Manual Flow Control
Select (MANUAL_FC_0) (or Port 1 Full-Duplex Manual Flow Control Select (MANUAL_FC_1)) is set. The currently
enabled duplex and flow control settings can also be monitored via this register. The flow control values in the Port x
Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV_x) are not affected by the values of the manual
flow control register. Refer to Section 10.5.1, "Flow Control Enable Logic," on page 226 for additional information.
9.3.2 VIRTUAL PHY IN MAC MODES
In the MAC modes of operation, an external PHY is connected to the MII interface. Because there is an external PHY
present, the Virtual PHY is not needed for external configuration. However, the switch fabric MAC still requires the
proper duplex and flow control settings. The RMII interface also requires the proper speed setting.
DS00001925A-page 182
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