LAN9353 Datasheet, PDF (342/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
11.3.2 DEVICE INITIALIZATION
Until the device has been initialized to the point where the various configuration inputs are valid, the I²C slave interface
will not respond to or be affected by any external pin activity.
11.3.2.1 I²C Slave Read Polling for Initialization Complete
Before device initialization, the I²C slave interface will not return valid data. To determine when the I²C slave interface
is functional, the Byte Order Test Register (BYTE_TEST) should be polled. Once the correct pattern is read, the inter-
face can be considered functional. At this point, the Device Ready (READY) bit in the Hardware Configuration Register
(HW_CFG) can be polled to determine when the device is fully configured.
Note: The Host should only use single register reads (one data cycle per I²C Start/Stop) while polling the
BYTE_TEST register.
11.3.3 ACCESS DURING AND FOLLOWING POWER MANAGEMENT
During any power management mode other than D0, reads and writes are ignored and the I²C slave interface will not
respond to or be affected by any external pin activity.
To determine when the I²C slave interface is functional, the Byte Order Test Register (BYTE_TEST) should be polled.
Once the correct pattern is read, the interface can be considered functional. At this point, the Device Ready (READY)
bit in the Hardware Configuration Register (HW_CFG) can be polled to determine when the device is fully configured.
Note: The Host should only use single register reads (one data cycle per I²C Start/Stop) while polling the
BYTE_TEST register.
11.3.4 I²C SLAVE READ SEQUENCE
Following the device addressing, as detailed in Section 11.3.1, a register is read from the device when the master sends
a start condition and control byte with the R/~W bit set. Assuming the slave address in the control byte matches the
device address, the control byte is acknowledged by the device. Otherwise, the entire sequence is ignored until the next
start condition. Following the acknowledge, the device sends 4 bytes of data. The first 3 bytes are acknowledged by the
master and on the fourth, the master sends a no-acknowledge followed by the stop condition. The no-acknowledge
informs the device not to send the next 4 bytes (as it would in the case of a multiple read). The internal register address
is unchanged following the single read.
Multiple reads are performed when the master sends an acknowledge on the fourth byte. The internal address is incre-
mented and the next register is shifted out. Once the internal address reaches its maximum, it rolls over to 0. The mul-
tiple read is concluded when the master sends a no-acknowledge followed by a stop condition. The no-acknowledge
informs the device not to send the next 4 bytes. The internal register address is incremented for each read including the
final.
For both single and multiple reads, in the case that the master sends a no-acknowledge on any of the first three bytes
of the register, the device will stop sending subsequent bytes. If the master sends an unexpected start or stop condition,
the device will stop sending immediately and will respond to the next sequence as needed.
I²C reads from unused register addresses return all zeros.
DS00001925A-page 342
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