LAN9353 Datasheet, PDF (140/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.2.20.13 PHY x Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x)
Index (decimal): 17
Size:
16 bits
This read/write register is used to control and monitor various PHY configuration options.
Bits
Description
15:14
13
RESERVED
Energy Detect Power-Down (EDPWRDOWN)
This bit controls the Energy Detect Power-Down mode.
Type
RO
R/W
0: Energy Detect Power-Down is disabled
1: Energy Detect Power-Down is enabled
Note:
When in EDPD mode, the device’s NLP characteristics can be
modified via the PHY x EDPD NLP / Crossover Time / EEE
Configuration Register (PHY_EDPD_CFG_x).
12:7 RESERVED
RO
6
ALTINT
Alternate Interrupt Mode:
R/W
NASR
0 = Primary interrupt system enabled (Default)
Note 16
1 = Alternate interrupt system enabled
Refer to Section 9.2.9, "PHY Interrupts," on page 105 for additional informa-
tion.
5:2 RESERVED
RO
1
Energy On (ENERGYON)
RO
Indicates whether energy is detected. This bit transitions to “0” if no valid
energy is detected within 256 ms (1500 ms if auto-negotiation is enabled). It
is reset to “1” by a hardware reset and by a software reset if auto-negotiation
was enabled or will be enabled via strapping. Refer to Section 9.2.10.2,
"Energy Detect Power-Down," on page 108 for additional information.
0
RESERVED
RO
Default
-
0b
-
0b
-
1b
-
Note 16: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Reg-
ister (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the
PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set.
DS00001925A-page 140
 2015 Microchip Technology Inc.