LAN9353 Datasheet, PDF (500/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
19.0 JTAG
19.1 JTAG
A IEEE 1149.1 compliant TAP Controller supports boundary scan and various test modes.
The device includes an integrated JTAG boundary-scan test port for board-level testing. The interface consists of four
pins (TDO, TDI, TCK and TMS) and includes a state machine, data register array, and an instruction register. The JTAG
pins are described in Table 3-12, “JTAG Pin Descriptions,” on page 36. The JTAG interface conforms to the IEEE Stan-
dard 1149.1 - 2001 Standard Test Access Port (TAP) and Boundary-Scan Architecture.
All input and output data is synchronous to the TCK test clock input. TAP input signals TMS and TDI are clocked into
the test logic on the rising edge of TCK, while the output signal TDO is clocked on the falling edge.
JTAG pins are multiplexed with the GPIO/LED and EEPROM pins. The JTAG functionality is selected when the TEST-
MODE pin is asserted.
The implemented IEEE 1149.1 instructions and their op codes are shown in Table 19-1.
TABLE 19-1: IEEE 1149.1 OP CODES
INSTRUCTION
BYPASS 0
BYPASS 1
SAMPLE/PRELOAD
EXTEST
CLAMP
ID_CODE
HIGHZ
INT_DR_SEL
OP CODE
16'h0000
16'hFFFF
16'hFFF8
16'hFFE8
16'hFFEF
16'hFFFE
16'hFFCF
16'hFFFD
COMMENT
Mandatory Instruction
Mandatory Instruction
Mandatory Instruction
Mandatory Instruction
Optional Instruction
Optional Instruction
Optional Instruction
Private Instruction
Note:
Note:
The JTAG device ID is 00121445h
All digital I/O pins support IEEE 1149.1 operation. Analog pins and the OSCI / OSCO pins do not support
IEEE 1149.1 operation.
DS00001925A-page 500
 2015 Microchip Technology Inc.