LAN9353 Datasheet, PDF (242/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.6.7 SWITCH FABRIC MAC ADDRESS LOW REGISTER (SWITCH_MAC_ADDRL)
Offset:
1F4h
Size:
32 bits
This register contains the lower 32 bits of the MAC address used by the switch for Pause frames. This register is used
in conjunction with Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH). The contents of this register
are optionally loaded from the EEPROM at power-on through the EEPROM Loader if a programmed EEPROM is
detected. The least significant byte of this register (bits [7:0]) is loaded from address 01h of the EEPROM. The most
significant byte (bits [31:24]) is loaded from address 04h of the EEPROM. The Host can update the contents of this field
after the initialization process has completed.
Refer to Section 12.4, "EEPROM Loader," on page 353 for information on using the EEPROM Loader.
Bits
Description
31:0 Physical Address[31:0]
This field contains the lower 32 bits (31:0) of the physical address of the
Switch Fabric MACs.
Type
R/W
Default
FF0F8000h
Table 10-7 illustrates the byte ordering of the SWITCH_MAC_ADDRL and SWITCH_MAC_ADDRH registers with
respect to the reception of the Ethernet physical address. Also shown is the correlation between the EEPROM
addresses and the SWITCH_MAC_ADDRL and SWITCH_MAC_ADDRH registers.
TABLE 10-7: SWITCH_MAC_ADDRL, SWITCH_MAC_ADDRH AND EEPROM BYTE ORDERING
EEPROM Address
Register Location Written
Order of Reception on Ethernet
01h
SWITCH_MAC_ADDRL[7:0]
1^st
02h
SWITCH_MAC_ADDRL[15:8]
2^nd
03h
SWITCH_MAC_ADDRL[23:16]
3^rd
04h
SWITCH_MAC_ADDRL[31:24]
4^th
05h
SWITCH_MAC_ADDRH[7:0]
5^th
06h
SWITCH_MAC_ADDRH[15:8]
6^th
For example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the SWITCH_MAC_ADDRL and
SWITCH_MAC_ADDRH registers would be programmed as shown in Figure 10-10. The values required to automati-
cally load this configuration from the EEPROM are also shown.
FIGURE 10-10: EXAMPLE SWITCH_MAC_ADDL, SWITCH_MAC_ADDRH AND EEPROM SETUP
31 24 23 16 15
87
0
xx
xx
BCh
9Ah
SWITCH_MAC_ADDRH
31 24 23 16 15
87
0
78h
56h
34h
12h
SWITCH_MAC_ADDRL
06h BCh
05h 9Ah
04h 78h
03h 56h
02h 34h
01h 12h
00h A5h
EEPROM
Note: By convention, the right nibble of the left most byte of the Ethernet address (in this example, the 2 of the
12h) is the most significant nibble and is transmitted/received first.
DS00001925A-page 242
 2015 Microchip Technology Inc.