LAN9353 Datasheet, PDF (102/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
Note: Auto-Negotiation is not used for 100BASE-FX mode.
The advertised capabilities of the PHY are stored in the PHY x Auto-Negotiation Advertisement Register (PHY_AN_AD-
V_x). The PHY contains the ability to advertise 100BASE-TX and 10BASE-T in both full or half-duplex modes. Besides
the connection speed, the PHY can advertise remote fault indication and symmetric or asymmetric pause flow control
as defined in the IEEE 802.3 specification. The transceiver supports “Next Page” capability which is used to negotiate
Energy Efficient Ethernet functionality as well as to support software controlled pages. Many of the default advertised
capabilities of the PHY are determined via configuration straps as shown in Section 9.2.20.5, "PHY x Auto-Negotiation
Advertisement Register (PHY_AN_ADV_x)," on page 129. Refer to Section 7.0, "Configuration Straps," on page 67 for
additional details on how to use the device configuration straps.
Once Auto-Negotiation has completed, information about the resolved link and the results of the negotiation process
are reflected in the Speed Indication bits in the PHY x Special Control/Status Register (PHY_SPECIAL_CON-
TROL_STATUS_x), as well as the PHY x Auto-Negotiation Link Partner Base Page Ability Register
(PHY_AN_LP_BASE_ABILITY_x). The Auto-Negotiation protocol is a purely physical layer activity and proceeds inde-
pendently of the MAC controller.
The following blocks are activated during an Auto-Negotiation session:
• Auto-Negotiation (digital)
• 100M ADC (analog)
• 100M PLL (analog)
• 100M equalizer/BLW/clock recovery (DSP)
• 10M SQUELCH (analog)
• 10M PLL (analog)
• 10M Transmitter (analog)
When enabled, Auto-Negotiation is started by the occurrence of any of the following events:
• Power-On Reset (POR)
• Hardware reset (RST#)
• PHY Software reset (via Reset Control Register (RESET_CTL), or bit 15 of the PHY x Basic Control Register
(PHY_BASIC_CONTROL_x))
• PHY Power-down reset (Section 9.2.10, "PHY Power-Down Modes," on page 108)
• PHY Link status down (bit 2 of the PHY x Basic Status Register (PHY_BASIC_STATUS_x) is cleared)
• Setting the PHY x Basic Control Register (PHY_BASIC_CONTROL_x), bit 9 high (auto-neg restart)
• Digital Reset (via bit 0 of the Reset Control Register (RESET_CTL))
• Issuing an EEPROM Loader RELOAD command (Section 12.4, "EEPROM Loader," on page 353) via EEPROM
Loader run sequence
Note: Refer to Section 6.2, "Resets," on page 51 for information on these and other system resets.
On detection of one of these events, the transceiver begins Auto-Negotiation by transmitting bursts of Fast Link Pulses
(FLP). These are bursts of link pulses from the 10M TX Driver. They are shaped as Normal Link Pulses and can pass
uncorrupted down CAT-3 or CAT-5 cable. A Fast Link Pulse Burst consists of up to 33 pulses. The 17 odd-numbered
pulses, which are always present, frame the FLP burst. The 16 even-numbered pulses, which may be present or absent,
contain the data word being transmitted. Presence of a data pulse represents a “1”, while absence represents a “0”.
The data transmitted by an FLP burst is known as a “Link Code Word.” These are defined fully in IEEE 802.3 clause 28.
In summary, the transceiver advertises 802.3 compliance in its selector field (the first 5 bits of the Link Code Word). It
advertises its technology ability according to the bits set in the PHY x Auto-Negotiation Advertisement Register
(PHY_AN_ADV_x).
There are 4 possible matches of the technology abilities. In the order of priority these are:
• 100M Full Duplex (Highest priority)
• 100M Half Duplex
• 10M Full Duplex
• 10M Half Duplex (Lowest priority)
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