HD64F2145 Datasheet, PDF (99/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

End of bus request
Bus request
End of bus
request
Bus-released state
End of
exception
handling
Program execution
state
Bus
request
Request for
exception
handling
SLEEP
instruction
with
LSON = 0,
PSS = 0,
SSBY = 1
SLEEP
instruction
with
LSON = 0,
SSBY = 0
Sleep mode
Exception-handling state
= high
Interrupt
request
External interrupt
request
Software standby mode
Reset state ^*1
= high,
= low
Hardware standby mode^*2
Power-down state^*3
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
2. From any state, a transition to hardware standby mode occurs when
goes low.
3. The power-down state also includes watch mode, subactive mode, subsleep mode, etc. For details,
refer to section 26, Power-Down Modes.
Figure 2.13 State Transitions
Rev. 2.0, 08/02, page 59 of 788