HD64F2145 Datasheet, PDF (494/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

16.5 Interrupt Sources
The IIC has interrupt sources IICI and DDCSWI. Table 16.8 shows the interrupt sources and
priority. Individual interrupt sources can be enabled or disabled using the enable bits in ICCR and
DDCSWR, and are sent to the interrupt controller independently.
An IICI interrupt can activate the DTC to allow data transfer.
Table 16.8 IIC Interrupt Sources
Channel
0
1
Name
IICI0
DDCS
WI
IICI1
Enable
Bit
IEIC
IE
IEIC
Interrupt Source
I²C bus interface
interrupt request
Format automatic
switch interrupt
I²C bus interface
interrupt request
Interrupt
Flag
IRIC
DTC Activation Priority
Possible
High
IF
Not possible
IRIC
Possible
Low
16.6 Usage Notes
1. In master mode, if an instruction to generate a start condition is issued and then an instruction
to generate a stop condition is issued before the start condition is output to the I²C bus, neither
condition will be output correctly. To output the start condition followed by the stop condition,
after issuing the instruction that generates the start condition, read DR in each I²C bus output
pin, and check that SCL and SDA are both low. The pin states can be monitored by reading
DR even if the ICE bit is set to 1. Then issue the instruction that generates the stop condition.
Note that SCL may not yet have gone low when BBSY is cleared to 0.
2. Either of the following two conditions will start the next transfer. Pay attention to these
conditions when accessing to ICDR.
 Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to
ICDRS)
 Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to
ICDRR)
3. Table 16.9 shows the timing of SCL and SDA outputs in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
Rev. 2.0, 08/02, page 454 of 788