HD64F2145 Datasheet, PDF (383/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

15.3.5 Serial Mode Register (SMR)
SMR is used to set the SCI’s serial transfer format and select the on-chip baud rate generator clock
source.
Bit
Bit Name Initial Value R/W Description
7
C/$
0
R/W Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode
6
CHR
0
R/W Character Length (enabled only in asynchronous
mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length. LSB-first is fixed
and the MSB of TDR is not transmitted in
transmission.
In clocked synchronous mode, a fixed data length of
8 bits is used.
5
PE
0
R/W Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity bit
is checked in reception. For a multiprocessor format,
parity bit addition and checking are not performed
regardless of the PE bit setting.
4
O/(
0
R/W Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
Rev. 2.0, 08/02, page 343 of 788