HD64F2145 Datasheet, PDF (190/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

7.5.7 Number of DTC Execution States
Table 7.5 lists the execution status for a single DTC data transfer, and table 7.6 shows the number
of states required for each execution status.
Table 7.5 DTC Execution Status
Mode
Register Information
Vector Read Read/Write
Data Read
I
J
K
Normal
1
6
1
Repeat
1
6
1
Block transfer 1
6
N
N: Block size (initial setting of CRAH and CRAL)
Data Write
L
1
1
N
Internal
Operations
M
3
3
3
Table 7.6 Number of States Required for Each Execution Status
On-Chip On-Chip On-Chip I/O
Object to be Accessed RAM ROM Registers
Bus width
32
16
8
16
Access states
1
1
2
2
2
Execution Vector read S —
1
I
status _Register
1
—
information
read/write S_J
Byte data read 1
1
S
K
Word data read 1
1
S_K
Byte data write 1
1
S
L
Word data 1
1
write S_L
Internal
operation S_M
—
—
4
—
—
—
2
2
2
4
2
4
2
2
2
4
2
4
1
External Devices
8
16
3
2
3
6 + 2m 2
3+m
—
—
—
3+m 2
6 + 2m 2
3+m 2
6 + 2m 2
3+m
3+m
3+m
3+m
The number of execution states is calculated from using the formula below. Note that Σ is the sum
of all transfers activated by one activation source (the number in which the CHNE bit is set to 1,
plus 1).
Number
of
execution
states
=
I
·
S
I
+
Σ
(J
·
S
J
+
K
·
S
K
+
L
·
S)
L
+
M
·
S
M
Rev. 2.0, 08/02, page 150 of 788