HD64F2145 Datasheet, PDF (487/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

When WAIT = 0, and FS = 0 or FSX = 0 (I²C bus format, no wait)
SCL
7
8
9
1
2
3
SDA
7
8
A
1
2
3
IRIC
User processing
Clear IRIC
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
SCL
7
8
9
1
SDA
7
8
A
1
IRIC
User processing
Clear IRIC
Write to ICDR (transmit)
or read from ICDR (receive)
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.
Figure 16.26 IRIC Setting Timing and SCL Control (1)
Clear IRIC
Rev. 2.0, 08/02, page 447 of 788