HD64F2145 Datasheet, PDF (501/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in
ICXR.
11. Note on ICDR read and ICCR access in slave transmit mode
In I²C bus interface slave transmit mode, do not read ICDR or do not read/write from/to ICCR
during the time shaded in figure 16.34. However, such read and write operations cause no
problem in interrupt handling processing that is generated in synchronization with the rising
edge of the 9th clock pulse because the shaded time has passed before making the transition to
interrupt handling.
To handle interrupts securely, be sure to keep either of the following conditions.
 Read ICDR data that has been received so far or read/write from/to ICCR before starting
the receive operation of the next slave address.
 Monitor the BC2 to BC0 bit counter in ICMR; when the count is 000 (8th or 9th clock
pulse), wait for at least two transfer clock times in order to read ICDR or read/write from/to
ICCR during the time other than the shaded time.
SDA
R/W
Waveform at problem occurrence
A
ICDR write
Bit 7
SCL
8
9
TRS bit
Address reception
Data transmission
ICDR read and ICCR read/write are disabled
(6 system clock period)
The rise of the 9th clock is detected
Figure 16.34 ICDR Read and ICCR Access Timing in Slave Transmit Mode
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in
ICXR.
Rev. 2.0, 08/02, page 461 of 788