HD64F2145 Datasheet, PDF (632/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

23.6 Operating Modes
The flash memory is connected to the CPU via a 16-bit data bus, enabling byte data and word data
to be accessed in a single state. Even addresses are connected to the upper 8 bits and odd addresses
are connected to the lower 8 bits. Note that word data must start from an even address.
On-chip ROM is enabled or disabled by the mode select pins (MD1 and MD0) and the EXPE bit
in MDCR, as summarized in table 23.3.
In normal mode (mode 3), up to 56 kbytes of ROM can be used.
Table 23.3 Operating Modes and ROM
MCU
Operating
Mode
Mode 1
Mode 2
Mode 3
Operating Modes
CPU
Operating
Mode
Mode
Normal
Expanded mode with
on-chip ROM disabled
Advanced
Single-chip mode
Advanced
Expanded mode with
on-chip ROM enabled
Normal
Single-chip mode
Normal
Expanded mode with
on-chip ROM enabled
Mode Pins
MD1
0
MD0
1
1
0
1
0
1
1
1
1
MDCR
EXPE
1
0
1
0
1
On-Chip
ROM
Disabled
Enabled
(64/128/256
kbytes)
Enabled
(56 kbytes)
23.7 On-Board Programming Modes
An on-board programming mode is used to perform on-chip flash memory programming, erasing,
and verification. This LSI has two on-board programming modes: boot mode and user program
mode. Table 23.4 shows pin settings for boot mode. In user program mode, operation by software
is enabled by setting control bits. For details on flash memory mode transitions, see figure 23.2.
Table 23.4 On-Board Programming Mode Settings
Mode Setting
MD1
MD0
P92
P91
P90
Boot mode
0
0
1*
1*
1*
User program Mode 2 (advanced mode) 1
0



mode
Mode 3 (normal mode)
1
1



Note:* Can be used as an I/O port after the boot mode activation.
Rev. 2.0, 08/02, page 592 of 788