HD64F2145 Datasheet, PDF (450/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 16.4 Flags and Transfer States (Master Mode)
MST TRS BBSY ESTP STOP IRTR AASX AL
1
1
0
0
0
0
0↓
0
1
1
1↑
0
0
1↑
0
0
1
—
1
0
0
—
0
0
1
1
1
0
0
—
0
0
1
1
1
0
0
1↑
0
0
1
1
1
0
0
—
0
0
1
1
1
0
0
—
0
0
1
1
1
0
0
—
0
0
1
1
1
0
0
1↑
0
0
1
0
1
0
0
1↑
0
0
1
0
1
0
0
—
0
0
1
0
1
0
0
—
0
0
1
0
1
0
0
—
0
0
1
0
1
0
0
1↑
0
0
AAS
0↓
0
0
0
0
0
0
0
0
0
0
0
0
0
ADZ
0↓
0
0
0
0
0
0
0
0
0
0
0
0
0
ACKB
0
0
—
1↑
0
0
0
0
0
—
—
—
—
—
ICDRF
—
—
—
—
—
—
—
—
—
1↑
0↓
1
0↓
1↑
ICDRE
0
1↑
—
—
1↑
0↓
1
0↓
1↑
—
—
—
—
—
State
Idle state (flag
clearing
required)
Start condition
detected
Wait state
Transmission
end (ACKE=1
and ACKB=1)
Transmission
end with
ICDRE=0
ICDR write
with the above
state
Transmission
end with
ICDRE=1
ICDR write
with the above
state or after
start condition
detected
Automatic
data transfer
from ICDRT to
ICDRS with
the above
state
Reception end
with ICDRF=0
ICDR read
with the above
state
Reception end
with ICDRF=1
ICDR read
with the above
state
Automatic
data transfer
from ICDRS to
ICDRR with
the above
state
Rev. 2.0, 08/02, page 410 of 788