HD64F2145 Datasheet, PDF (275/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 10.3 summarizes the relationships between the CKS, CFS, and OS bit settings and the
resolution, base cycle, and conversion cycle. The PWM output remains fixed unless DADR
contains at least a certain minimum value.
Table 10.3 Settings and Operation (Examples when ø = 10 MHz)
Fixed DADR Bits
Resolution
Base
Conversion T_L (if OS = 0)
CKS T (µs)
CFS Cycle (µs) Cycle (µs) T_H (if OS = 1)
0 0.1
0 6.4
1638.4
1. Always low (or high)
(DADR = H'0001 to
H'03FD)
2. (Data value) × T
(DADR = H'0401 to
H'FFFD)
Precisi- Bit Data
on
Conversion
(Bits) 3 2 1 0 Cycle* (µs)
14
1638.4
12
0 0 409.6
10
0 0 0 0 102.4
1 25.6
1. Always low (or high) ₁₄
(DADR = H'0003 to ₁₂
H'00FF)
2. (Data value) × T
(DADR = H'0103 to 10
H'FFFF)
1638.4
0 0 409.6
0 0 0 0 102.4
1 0.2
0 12.8
3276.8
1. Always low (or high) 14
(DADR = H'0001 to
H'03FD)
12
2. (Data value) × T
(DADR = H'0401 to ₁₀
H'FFFD)
3276.8
0 0 819.2
0 0 0 0 204.8
1 51.2
1. Always low (or high) 14
(DADR = H'0003 to
H'00FF)
12
2. (Data value) × T
10
(DADR = H'0103 to
H'FFFF)
3276.8
0 0 819.2
0 0 0 0 204.8
Note:* This column indicates the conversion cycle when specific DADR bits are fixed.
Rev. 2.0, 08/02, page 235 of 788