HD64F2145 Datasheet, PDF (164/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

16-Bit, 2-State Access Space: Figures 6.7 to 6.9 show bus timings for a 16-bit, 2-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states cannot be
inserted.
Bus cycle
T₁
T₂
Ø
Address bus
/ (IOSE = 1)
/ (IOSE = 0)
Read D15 to D8
D7 to D0
Valid
Invalid
Write
D15 to D8
High level
Valid
D7 to D0
Undefined
Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access)
Rev. 2.0, 08/02, page 124 of 788