HD64F2145 Datasheet, PDF (312/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

12.3.4 Timer Control Register (TCR)
TCR selects the TCNT clock source and the condition by which TCNT is cleared, and
enables/disables interrupt requests.
Bit Bit Name Initial Value R/W Description
7
CMIEB 0
R/W Compare-Match Interrupt Enable B
Selects whether the CMFB interrupt request (CMIB) is
enabled or disabled when the CMFB flag in TCSR is set to
1. Note that a CMIB interrupt is not generated by TMR_X,
regardless of the CMIEB value.
0: CMFB interrupt request (CMIB) is disabled
1: CMFB interrupt request (CMIB) is enabled
6
CMIEA 0
R/W Compare-Match Interrupt Enable A
Selects whether the CMFA interrupt request (CMIA) is
enabled or disabled when the CMFA flag in TCSR is set to
1. Note that a CMIA interrupt is not generated by TMR_X,
regardless of the CMIEA value.
0: CMFA interrupt request (CMIA) is disabled
1: CMFA interrupt request (CMIA) is enabled
5
OVIE
0
R/W Timer Overflow Interrupt Enable
Selects whether the OVF interrupt request (OVI) is enabled
or disabled when the OVF flag in TCSR is set to 1. Note
that an OVI interrupt is not generated by TMR_X,
regardless of the OVIE value.
0: OVF interrupt request (OVI) is disabled
1: OVF interrupt request (OVI) is enabled
Rev. 2.0, 08/02, page 272 of 788