HD64F2145 Datasheet, PDF (532/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

18.3.5 Status Register (STR)
STR indicates status information during host interface processing.
Bit
7 to 4
Bit
Name
DBU
3
C/'
Initial
Value
All 0
R/W
Slave Host
R/W
R
0
R
R
2
DBU
0
R/W
R
1
IBF
0
R
R
0
OBF
0
R/(W)* R
Note:* Only 0 can be written, to clear the flag.
Description
Defined by User
The user can use these bits as necessary.
Command/Data
Receives the HA0 input when the host
processor writes to IDR, and indicates whether
IDR contains data or a command.
0: Contents of input data register (IDR) are data
1: Contents of input data register (IDR) are a
command
Defined by User
The user can use these bits as necessary.
Input Buffer Full
This bit is an internal interrupt source to the
slave processor (this LSI).
The IBF flag setting and clearing conditions are
different when the fast A20 gate is used. For
details see table 18.5.
[Clearing Condition]
0: When the slave processor reads IDR
[Setting Condition]
1: When the host processor writes to IDR
Output Buffer Full
[Clearing Condition]
0: When the host processor reads ODR or the
slave writes 0 in the OBF bit
[Setting Condition]
1: When the slave processor writes to ODR
Rev. 2.0, 08/02, page 492 of 788