HD64F2145 Datasheet, PDF (435/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Figure 16.1 shows a block diagram of the I²C bus interface. Figure 16.2 shows an example of I/O
pin connections to external circuits. Since I²C bus interface I/O pins are different in structure from
normal port pins, they have different specifications for permissible applied voltages. For details,
see section 28, Electrical Characteristics.
Formatless dedicated
clock (IIC_0 only)
ICXR
ø
PS
SCL
Noise
canceler
SDA
Noise
canceler
Clock
control
Bus state
decision
circuit
Arbitration
decision
circuit
Output data
control
circuit
ICCR
ICMR
ICSR
ICDRT
ICDRS
ICDRR
Address
comparator
SAR, SARX
Legend:
ICCR: I2C bus control register
ICMR: I2C bus mode register
ICSR: I2C bus status register
ICDR: I2C bus data register
ICXR: I2C bus extended control register
SAR: Slave address register
SARX: Slave address register X
PS: Prescaler
Interrupt
generator
Figure 16.1 Block Diagram of I²C Bus Interface
Interrupt
request
Rev. 2.0, 08/02, page 395 of 788