HD64F2145 Datasheet, PDF (157/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

6.4 Bus Control
6.4.1 Bus Specifications
The external address space bus specifications consist of three elements: Bus width, the number of
access states, and the wait mode and the number of program wait states. The bus width and the
number of access states for on-chip memory and internal I/O registers are fixed, and are not
affected by the bus controller settings.
Bus Width: A bus width of 8 or 16 bits can be selected via the ABW bit in WSCR.
Number of Access States: Two or three access states can be selected via the AST bit in WSCR.
When the 2-state access space is designated, wait-state insertion is disabled.
In the burst ROM interface, the number of access states is determined regardless of the AST bit
setting.
Wait Mode and Number of Program Wait States: When a 3-state access space is designated by
the AST bit in WSCR, the wait mode and the number of program wait states to be inserted
automatically is selected by the WMS1, WMS0, WC1, and WC0 bits in WSCR. From 0 to 3
program wait states can be selected.
Rev. 2.0, 08/02, page 117 of 788