HD64F2145 Datasheet, PDF (541/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

host, clearing by the host is held pending during the P4DR or PBODR read/write by the CPU.
P4DR or PBODR clearing is executed after completion of the read/write.
18.6 Usage Notes
18.6.1 Note on Host Interface
The host interface provides buffering of asynchronous data from the host processor and slave
processor (this LSI), but an interface protocol must be followed to implement necessary functions
and avoid data contention. For example, if the host and slave processors try to access the same
input or output data register simultaneously, the data will be corrupted. Interrupts can be used to
design a simple and effective protocol.
Also, if two or more of pins &64 to &67 are driven low simultaneously in attempting IDR or ODR
access, signal contention will occur within the chip, and a through-current may result. This usage
must therefore be avoided.
18.6.2 Module Stop Mode Setting
XBS operation can be enabled or disabled using the module stop control register. The initial
setting is for XBS operation to be halted. Register access is enabled by canceling module stop
mode. For details, refer to section 26, Power-Down Modes.
Rev. 2.0, 08/02, page 501 of 788