HD64F2145 Datasheet, PDF (641/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

START _*1
Set SWE bit in FLMCR1
Wait (x) µs
*²
n=1
Set EBR1 and EBR2
*⁴
Enable WDT
Set ESU bit in FLMCR2
Wait (y) µs
Set E bit in FLMCR1
Wait (z) ms
Clear E bit in FLMCR1
Wait (α) µs
Clear ESU bit in FLMCR2
*²
Start of erasing
*²
End of erasing
*²
Wait (β) µs
*²
Disable WDT
Set EV bit in FLMCR1
Wait (γ) µs
*²
Set block start address
as verify address
n¬n + 1
Increment
address
H'FF dummy write to verify address
Wait (ε) µs
*²
Read verify data
*³
Verify data
NG
= all "1"?
OK
NG
Last address
of block?
OK
Clear EV bit in FLMCR1
Clear EV bit in FLMCR1
Wait (η) µs
*²
NG ^*5
All erase blocks erased?
Wait (η) µs
n≥ (N) ?
*²
*² _NG
OK
Clear SWE bit in FLMCR1
OK
Clear SWE bit in FLMCR1
Wait (θ) µs
Wait (θ) µs
End of erasing
Erase failure
Notes:
1. Prewriting (writing 0 to all data in erased block) is not necessary.
2. The values of x, y, z, α, β, γ, ε, η, θ, and N are shown in section 28, Flash Memory Characteristics.
3. Verify data is read in 16-bit (word) units.
4. Set only a single bit in EBR1 and EBR2. Do not set more than one bit.
5. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
Figure 23.12 Erase/Erase-Verify Flowchart
Rev. 2.0, 08/02, page 601 of 788