HD64F2145 Datasheet, PDF (531/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

18.3.3 Input Data Register (IDR)
IDR is a register in which data to be input from the host processor to the slave processor (this LSI)
is stored.
Bit
Bit Name
7
IDR7
6
IDR6
5
IDR5
4
IDR4
3
IDR3
2
IDR2
1
IDR1
0
IDR0
Initial
Value








R/W
Slave Host
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Description
When &6Q (n = 1 to 4) is low, information on the
host data bus is written into IDR_n at the rising
edge of ,2:. The HA0 state is also latched into
the C/' bit in STR_n to indicate whether the
written information is a command or data.
18.3.4 Output Data Register 1 (ODR)
ODR is a register in which data to be output from the slave processor (this LSI) to the host
processor is stored.
Bit
Bit Name
7
ODR7
6
ODR6
5
ODR5
4
ODR4
3
ODR3
2
ODR2
1
ODR1
0
ODR0
Initial
Value








R/W
Slave Host
R/W R
R/W R
R/W R
R/W R
R/W R
R/W R
R/W R
R/W R
Description
The ODR_n contents are output on the host
data bus when HA0 is low, &6Q (n = 1 to 4) is
low, and ,25 is low.
Rev. 2.0, 08/02, page 491 of 788