HD64F2145 Datasheet, PDF (454/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

16.3.6 I²C Bus Status Register (ICSR)
ICSR consists of status flags. Also see tables 16.4 and 16.5.
Bit Bit Name Initial Value R/W Description
7 ESTP
0
R/(W)* Error Stop Condition Detection Flag
This bit is valid in I²C bus format slave mode.
[Setting condition]
When a stop condition is detected during frame transfer.
[Clearing conditions]
• When 0 is written in ESTP after reading ESTP = 1
• When the IRIC flag in ICCR is cleared to 0
6 STOP
0
R/(W)* Normal Stop Condition Detection Flag
This bit is valid in I²C bus format slave mode.
[Setting condition]
When a stop condition is detected after frame transfer
completion.
[Clearing conditions]
5 IRTR
0
• When 0 is written in STOP after reading STOP = 1
• When the IRIC flag is cleared to 0
R/(W)* I²C Bus Interface Continuous Transfer Interrupt Request
Flag
Indicates that the I²C bus interface has issued an interrupt
request to the CPU, and the source is completion of
reception/transmission of one frame in continuous
transmission/reception for which DTC activation is possible.
When the IRTR flag is set to 1, the IRIC flag is also set to 1
at the same time.
[Setting conditions]
I²C bus format slave mode:
• When the ICDRE or ICDRF flag in ICDR is set to 1
when AASX = 1
Master mode or clocked synchronous serial format mode
with I²C bus format, or formatless mode:
• When the ICDRE or ICDRF flag is set to 1
[Clearing conditions]
• When 0 is written after reading IRTR = 1
• When the IRIC flag is cleared to 0 while ICE is 1
Rev. 2.0, 08/02, page 414 of 788