HD64F2145 Datasheet, PDF (491/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 16.7 Examples of Operation Using DTC
Item
Master Transmit Master Receive Slave Transmit Slave Receive
Mode
Mode
Mode
Mode
Slave address + Transmission by
R/: bit
DTC (ICDR write)
transmission/
reception
Transmission by
CPU (ICDR write)
Reception by
CPU (ICDR read)
Reception by CPU
(ICDR read)
Dummy data —
Processing by
—
—
read
CPU (ICDR read)
Actual data
transmission/
reception
Transmission by Reception by
Transmission by Reception by DTC
DTC (ICDR write) DTC (ICDR read) DTC (ICDR write) (ICDR read)
Dummy data —
—
Processing by
—
(H'FF) write
DTC (ICDR write)
Last frame
processing
Not necessary
Reception by
Not necessary
CPU (ICDR read)
Reception by CPU
(ICDR read)
Transfer request 1st time: Clearing Not necessary
processing after by CPU
last frame
processing
2nd time: Stop
condition issuance
by CPU
Automatic clearing Not necessary
on detection of stop
condition during
transmission of
dummy data (H'FF)
Setting of
number of DTC
transfer data
frames
Transmission:
Reception: Actual
Actual data count data count
+ 1 (+1 equivalent
to slave address +
R/: bits)
Transmission:
Actual data count
+ 1 (+1 equivalent
to dummy data
(H'FF))
Reception: Actual
data count
16.4.10 Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 16.29 shows a block diagram of the noise canceler.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) pin
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Rev. 2.0, 08/02, page 451 of 788