HD64F2145 Datasheet, PDF (423/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Transmission: During transmission, the output signals from the SCI (UART frames) are
converted to IR frames using the IrDA interface (see figure 15.22).
For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is
output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in
KBCOMP.
The high-level pulse width is defined to be 1.41 µs at minimum and (3/16 + 2.5%) × bit rate or
(3/16 × bit rate) + 1.08 µs at maximum. For example, when the frequency of system clock ø is 20
MHz, a high-level pulse width of at least 1.4 µs to 1.6 µs can be specified.
For serial data of level 1, no pulses are output.
Start
bit
UART frame
Data
Stop
bit
0
1
0
1
0
0
1
1
0
1
Transmission
Reception
Start
bit
01
IR frame
Data
01
0
01
1
Stop
bit
01
Bit
cycle
Pulse width is 1.6 s to
3/16 bit cycle
Figure 15.22 IrDA Transmission and Reception
Reception: During reception, IR frames are converted to UART frames using the IrDA interface
before inputting to SCI_2.
Data of level 0 is output each time a high-level pulse is detected and data of level 1 is output when
no pulse is detected in a bit cycle. If a pulse has a high-level width of less than 1.41 µs, the
minimum width allowed, the pulse is recognized as level 0.
High-Level Pulse Width Selection: Table 15.10 shows possible settings for bits IrCKS2 to
IrCKS0 (minimum pulse width), and this LSI's operating frequencies and bit rates, for making the
pulse width shorter than 3/16 times the bit rate in transmission.
Rev. 2.0, 08/02, page 383 of 788