HD64F2145 Datasheet, PDF (177/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

7.2.1 DTC Mode Register A (MRA)
MRA selects the DTC operating mode.
Bit Bit Name Initial Value R/W Description
7 SM1
Undefined — Source Address Mode 1, 0
6 SM0
Undefined — These bits specify an SAR operation after a data
transfer.
0X: SAR is fixed
10: SAR is incremented after a transfer
(by +1 when Sz = 0, by +2 when Sz = 1)
11: SAR is decremented after a transfer
(by –1 when Sz = 0, by –2 when Sz = 1)
5 DM1
Undefined — Destination Address Mode 1, 0
4 DM0
Undefined — These bits specify a DAR operation after a data
transfer.
0X: DAR is fixed
10: DAR is incremented after a transfer
(by +1 when Sz = 0, by +2 when Sz = 1)
11: DAR is decremented after a transfer
(by –1 when Sz = 0, by –2 when Sz = 1)
3 MD1
Undefined — DTC Mode
2 MD0
Undefined — These bits specify the DTC transfer mode.
00: Normal mode
01: Repeat mode
10: Block transfer mode
11: Setting prohibited
1 DTS
Undefined — DTC Transfer Mode Select
Specifies whether the source side or the destination
side is set to be a repeat area or block area in repeat
mode or block transfer mode.
0: Destination side is repeat area or block area
1: Source side is repeat area or block area
0 Sz
Undefined — DTC Data Transfer Size
Specifies the size of data to be transferred.
0: Byte-size transfer
1: Word-size transfer
Legend:
X: Don't care
Rev. 2.0, 08/02, page 137 of 788