HD64F2145 Datasheet, PDF (328/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Input Capture Signal Input Timing: Figure 12.11 shows the timing of the input capture
operation.
ø
TMRIX
Input capture
signal
TCNTX
n
n+1
N
N+1
TICRR
M
n
n
TICRF
m
m
N
Figure 12.11 Timing of Input Capture Operation
If the input capture signal is input while TICRR and TICRF are being read, the input capture
signal is delayed by one system clock (ø) cycle. Figure 12.12 shows the timing of this operation.
TICRR, TICRF read cycle
T₁
T₂
ø
TMRIX
Input capture
signal
Figure 12.12 Timing of Input Capture Signal
(Input capture signal is input during TICRR and TICRF read)
Rev. 2.0, 08/02, page 288 of 788