HD64F2145 Datasheet, PDF (380/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Clocked Synchronous Mode:
• Data length: 8 bits
• Receive error detection: Overrun errors
• Serial data communication with other LSIs that have the clock synchronized communication
function
A block diagram of the SCI is shown in figure 15.1.
Module data bus
RxD
TxD
SCK
RDR
RSR
TDR
TSR
SCMR
SSR
SCR
SMR
BRR
Baud rate
generator
Transmission/
reception control
Parity generation
Clock
Parity check
External clock
ø
ø/4
ø/16
ø/64
Legend
RSR : Receive shift register
RDR : Receive data register
TSR : Transmit shift register
TDR : Transmit data register
SMR : Serial mode register
TEI
TXI
RXI
ERI
SCR
SSR
SCMR
BRR
: Serial control register
: Serial status register
: Smart card mode register
: Bit rate register
Figure 15.1 Block Diagram of SCI
Rev. 2.0, 08/02, page 340 of 788