HD64F2145 Datasheet, PDF (347/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

13.3.4 Edge Sense Register (SEDGR)
SEDGR detects a rising edge on the timer connection input pins and the occurrence of 2fH
modification, and determines the phase of the IVI and IHI signals.
Bit
Bit Name Initial Value R/W Description
7
VEDG
0
R/(W)*¹ VSYNCI Edge
Detects a rising edge on the VSYNCI pin.
[Clearing condition]
When 0 is written in VEDG after reading VEDG = 1
[Setting condition]
When a rising edge is detected on the VSYNCI pin
6
HEDG
0
R/(W)*¹ HSYNCI Edge
Detects a rising edge on the HSYNCI pin.
[Clearing condition]
When 0 is written in HEDG after reading HEDG = 1
[Setting condition]
When a rising edge is detected on the HSYNCI pin
5
CEDG
0
R/(W)*¹ CSYNCI Edge
Detects a rising edge on the CSYNCI pin.
[Clearing condition]
When 0 is written in CEDG after reading CEDG = 1
[Setting condition]
When a rising edge is detected on the CSYNCI pin
4
HFEDG 0
R/(W)*¹ HFBACKI Edge
Detects a rising edge on the HFBACKI pin.
[Clearing condition]
When 0 is written in HFEDG after reading HFEDG = 1
[Setting condition]
When a rising edge is detected on the HFBACKI pin
3
VFEDG 0
R/(W)*¹ VFBACKI Edge
Detects a rising edge on the VFBACKI pin.
[Clearing condition]
When 0 is written in VFEDG after reading VFEDG = 1
[Setting condition]
When a rising edge is detected on the VFBACKI pin
Rev. 2.0, 08/02, page 307 of 788