HD64F2145 Datasheet, PDF (264/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

• PWOERB
Bit Bit Name Initial Value R/W
7 OE15
0
R/W
6 OE14
0
R/W
5 OE13
0
R/W
4 OE12
0
R/W
3 OE11
0
R/W
2 OE10
0
R/W
1 OE9
0
R/W
0 OE8
0
R/W
Legend
X: Don't care
Description
Output Enable 15 to 8
These bits, together with P2DDR, specify the P2n/PWn
pin state. Bits OE15 to OE8 correspond to outputs
PW15 to PW8.
P2nDDR OEn: Pin state
0X: Port input
10: Port output or PWM 256/256 output
11: PWM output (0 to 255/256 output)
To perform PWM 256/256 output when DDR = 1 and OE = 0, the corresponding pin should be set
to port output. The corresponding pin can be set as port output in single-chip mode or when IOSE
= 1 and CS256E = 0 in SYSCR in extended mode with on-chip ROM. Otherwise, it should be
noted that an address bus is output to the corresponding pin.
DR data is output when the corresponding pin is used as port output. A value corresponding to
PWM 256/256 output is determined by the OS bit, so the value should have been set to DR
beforehand.
9.3.5 Peripheral Clock Select Register (PCSR)
PCSR selects the PWM input clock.
Bit Bit Name
3—
2 PWCKB
1 PWCKA
0—
Initial Value R/W
0
R
0
R/W
0
R/W
0
R
Description
Reserved
This bit is always read as 0. The initial value should not
be changed.
PWM Clock Select B, A
Together with bits PWCKE and PWCKS in PWSL,
these bits select the internal clock input to TCNT in the
PWM. For details, see table 9.2.
Reserved
This bit is always read as 0. The initial value should not
be changed.
Rev. 2.0, 08/02, page 224 of 788