HD64F2145 Datasheet, PDF (150/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

(1) When a break address specified instruction is executed for one state in the program area and on-chip memory
Instruction Instruction Instruction Instruction Instruction Internal
fetch
fetch
fetch
fetch
fetch operation
Save
to stack
Vector Internal Instruction
fetch ^{operation fetch}
Address bus
H'0310 H'0312 H'0314 H'0316 H'0318
SP-2 SP-4
H'0036
Break request
signal
NOP
NOP
NOP
execution execution execution
Interrupt exception handling
H'0310
H'0312
H'0314
H'0316
NOP
NOP
NOP
NOP
Break point
NOP instruction is executed at break point address
H'0312 and following address H'0314.
Fetching is performed from address H'0316
after exception handling ends.
(2) When a break address specified instruction is executed for two states in the program area and on-chip memory
Instruction Instruction Instruction Instruction Instruction Internal
fetch
fetch
fetch
fetch
fetch operation
Save
to stack
Vector Internal Instruction
fetch ^{operation fetch}
Address bus
H'0310 H'0312 H'0314 H'0316 H'0318
SP-2 SP-4
H'0036
NOP
MOV.W
execution execution
Break request
signal
H'0310 NOP
H'0312 MOV.W #xx:16,Rd
H'0316 NOP
H'0318 NOP
Break point
Interrupt exception handling
MOV instruction is executed at break point address
H'0312, and NOP instruction is not executed
at the following address H'0314.
Fetching is performed from address H'0316
after exception handling ends.
(3) When a break address specified instruction is executed for one state in the program area
and external memory (2-state access, 16-bit bus access)
Instruction
fetch
Instruction Instruction Internal Save
fetch
fetch
operation _{to stack}
Vector
fetch
Instruction
fetch
Address bus
H'0310
H'0312
H'0314
SP-2 SP-4 H'0036
Break request
signal
NOP
execution
Interrupt exception handling
H'0310 NOP
H'0312 NOP
H'0314 NOP
H'0316 NOP
Break point
NOP instruction is not executed at break point address H'0312.
Fetching is performed from address H'0312
after exception handling ends.
Figure 5.10 Address Break Timing Example
Rev. 2.0, 08/02, page 110 of 788