HD64F2145 Datasheet, PDF (555/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

R/W
Bit Bit Name Initial Value Slave Host Description
4 ABRT 0
R/(W)* — LPC Abort Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when a forced termination (abort) of an LPC transfer
cycle occurs.
0: [Clearing conditions]
• Writing 0 after reading ABRT = 1
• LPC hardware reset and LPC software reset
• LPC hardware shutdown and LPC software
shutdown
1: [Setting condition]
• /)5$0( pin falling edge detection during LPC
transfer cycle
3 IBFIE3 0
R/W — IDR3 and TWR Receive Completion Interrupt
Enable
Enables or disables IBFI3 interrupt to the slave
processor (this LSI).
0: Input data register IDR3 and TWR receive
completed interrupt requests disabled
1: [When TWRIE = 0 in LADR3]
Input data register (IDR3) receive completed
interrupt requests enabled
[When TWRIE = 1 in LADR3]
Input data register (IDR3) and TWR receive
completed interrupt requests enabled
2 IBFIE2 0
R/W — IDR2 Receive Completion Interrupt Enable
Enables or disables IBFI2 interrupt to the slave
processor (this LSI).
0: Input data register (IDR2) receive completed
interrupt requests disabled
1: Input data register (IDR2) receive completed
interrupt requests enabled
1 IBFIE1 0
R/W — IDR1 Receive Completion Interrupt Enable
Enables or disables IBFI1 interrupt to the slave
processor (this LSI).
0: Input data register (IDR1) receive completed
interrupt requests disabled
1: Input data register (IDR1) receive completed
interrupt requests enabled
Rev. 2.0, 08/02, page 515 of 788