HD64F2145 Datasheet, PDF (331/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

12.9 Usage Notes
12.9.1 Conflict between TCNT Write and Clear
If a counter clear signal is generated during the T2 state of a TCNT write cycle as shown in figure
12.14, clearing takes priority, so that the counter is cleared and the write is not performed.
TCNT write cycle by CPU
T1
T2
Ø
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
H'00
Figure 12.14 Conflict between TCNT Write and Clear
Rev. 2.0, 08/02, page 291 of 788